The present invention relates to flash memory systems, and more particularly to internally transferring data from one portion of a flash memory device to another portion of the flash memory device.
FIG. 1 is a block diagram of a flash memory device 100. The flash memory 100 includes several signal lines, including a power line 110, a erase power line 111, a plurality of address lines 112, a plurality of data lines 113, and a plurality of control lines 114. The plurality of control lines may comprise well known control signals, such as row and column address strobes, clock signals, write enable signals, and chip select signals, which are not individually shown in order to avoid cluttering the figure. As is well known in the art, the state of the signals on the plurality of control lines 114 may be used to designate commands. These commands include a READ command for reading data, a WRITE command for writing data, and an ERASE command for erasing a block.
Commands are decoded by a command execution logic 120, which in cooperation with a state machine 121, cause the flash memory device 100 to execute the asserted commands. The data within the flash memory device is stored in a memory array 160, which is organized into a plurality of blocks 161-162. Each block 161-162 is typically comprised of a plurality of sectors 161a, 161b, 162a, 162b which store one or more bytes of data. The memory array 160 may be accessed through the addressing and I/O circuit 140, which includes a device buffer 150. The device buffer 150 can vary in size but must have a minimum capacity of at least the data which can be stored in a sector of the flash memory device. Additionally, the erase power may be supplied to the memory array 160 via the erase voltage switch 130. The state of the switch 130 is controlled by the state machine 121.
While FIG. 1 shows only a single memory array 160 with two blocks 161-162, it should be understood that flash memories may include multiple arrays, or banks, each having more than two blocks. For example, one commercially available 64 Mb flash memory device available from the assignee of this invention is organized into four banks each having a 4096 by 256 array of 16-bit sectors. Each bank of this flash memory is divided into four blocks, therefore the flash memory device has sixteen blocks.
Flash memories are non-volatile memories implemented using floating gates. The presence or absence of a charge on the floating gate is used to indicate whether a bit is a binary xe2x80x9c0xe2x80x9d or a binary xe2x80x9c1xe2x80x9d. Flash memories are further characterized by the fact that each bit may always be changed from a first state to a second state. The only way to change a bit from the second state to the first state is to use the erase operation. However, the erase operation also erases every other bit in the block.
The requirement to erase an entire block when changing a bit from the second state to the first state greatly complicates writing to a flash memory. If data is written to a newly erased or a previously unwritten address, the data may simply be written into the specified address. However, writing data to an address which was previously written requires a four step process. First, each sector (other than the sector to be written with new data) within that block must be backed up. Second, the block is erased. Third, the backed up data is written to the newly erased sector. Finally, the new data is written.
This process is illustrated in FIGS. 2A, 2B, 3A and 3B. FIGS. 2A and 2B are simplified block diagrams of the flash memory device 100 coupled to a controller 200 via a bus 300. The diagrams are simplified by only illustrating certain components of the flash memory device 100 and the controller 200, specifically memory blocks 161, 162, the device buffer 150, and sectors 161a, 161b, 162a of the flash memory device 100 and the buffer 201 of the controller 200. Additionally, FIGS. 2A and 2B include arrows showing data transfers. These data transfers are sequentially labeled with numbers located within parenthesis showing the order of the data transfer. FIGS. 3A and 3B are timing diagrams illustrating the processes shown in FIGS. 2A and 2B and contains the same labels to identify the data transfer events on the timing diagram.
Referring now to FIGS. 2A and 3A, suppose sectors 161a and 161b contain data (i.e., were previously written) and new data is to be written into sector 161b. The process begins when the controller 200 issues a read command to sector 161a. The first data transfer (1) is from sector 161a to the device buffer 150. The second data transfer (2) is from the device buffer 150 to the controller buffer 201. As shown in FIG. 3A, data transfers (1) and (2) begin when the controller 200 asserts a READ command on the control line 114, while asserting the address of sector 161a on the address lines 112, and ends when the flash memory device 100 outputs the xe2x80x9cOLDxe2x80x9d data contained sector 161a onto the data lines 113 (FIG. 1).
At this point, the controller 200 can write the data in sector 161a to another sector 162a in a different block 162. Thus, the third data transfer (3) is from the controller buffer 201 to the device buffer 150. The fourth data transfer (4) is from the device buffer 150 to sector 162a. As shown in FIG. 3A, data transfers (3) and (4) begin when the controller 200 asserts a WRITE command on control lines 114, the address associated with sector 162a on the address lines 112, and the xe2x80x9cOLDxe2x80x9d data on data lines 113. The first through fourth data transfers are repeated, as necessary, until each sector in block 161 which contains data is transferred to block 162. The only exception is the sector which is to be written with new data. In this example, only sector 161a required copying to an alternate block. Thus, at this point block 161 can be erased. As shown in FIG. 3A, this occurs when the controller 200 asserts the ERASE command on the control lines 114 and the address of block 161 on the address lines 112. The erase command causes every bit in block 161 to be set to the first state, and can take a significant amount of time to complete.
Once block 161 has been erased, the contents of the block (except for the sector receiving the new data) needs to be restored. This process is illustrated in FIG. 2B and 3B, and begins with the fifth data transfer (5), which copies data from sector 162a to the device buffer 150. The sixth data transfer (6) is from the device buffer 150 to the controller buffer 201. As shown in FIG. 3B, data transfers (5) and (6) begin when the controller asserts the READ command on the control lines 114 and the address of sector 162a on the address lines 112, and ends when the flash memory device 100 outputs the xe2x80x9cOLDxe2x80x9d data on the data lines 113 (FIG. 1).
Now the controller 200 can write the data back to block 161. Thus, the seventh data transfer (7) is between the controller buffer 201 and the device buffer 150. Finally, the eighth data transfer (8) writes the data from the device buffer 150 to sector 161a. As shown in FIG. 3B, data transfers (7) and (8) begin when the controller 200 asserts the WRITE command on control lines 114 , the address of sector 161a on address lines 112, and the xe2x80x9cOLDxe2x80x9d data on data lines 113. This process is repeated for each sector which was copied from block 161 to block 162. In this example, only sector 162a required copying.
Finally, the new data can be written into sector 161b. This is shown in FIG. 3B when the controller 200 asserts the WRITE command on control lines 114, the address of sector 161b on address lines 112, and the xe2x80x9cNEWxe2x80x9d data on data lines 113. Alternatively, the new data can be written prior to restoring the old data.
The above process is problematic for at least two reasons. First, the controller""s 200 buffer 201 cannot be used for any other purpose during this operation. Additionally, two off chip data transfers were required. Accordingly, there is a need for a flash memory device which is capable of internally copying data from one block to another block.
The present invention is directed to a flash memory device which supports a new command for internally reading a sector of data from one address of the flash memory device and writing that data to a different sector of the flash memory. In one embodiment, the command includes an option to transfer a plurality of sectors. Since the source and destination addresses are supplied as part of the command, there is no need to transfer the data off chip. Consequently, there is no need for an external flash controller to oversee the data transfer. The present invention allows use of a less complex external flash controller and it also reduces bus traffic, thereby improving system performance. Additionally, by reducing the need to drive data over the bus, a significant reduction in power consumption may be achieved, in both the memory controller and the memory device.